Field of the Invention
The present invention relates to an integrated semiconductor memory having memory cells for storing data signals, having a sense amplifier, a signal line and a memory circuit.
More recent generations of integrated semiconductor memories have an increasing integration density and an increasing number of integrated functions. A semiconductor memory is usually connected to further components which together form a computer system, for example. For semiconductor memories which have relatively large dimensions and relatively long conductor tracks it is becoming more and more difficult to achieve the data access times which are required by components which switch at high speed, for example the computer system.
A data access can usually be divided into a plurality of function blocks. In a first function block, access commands are decoded and the respective memory cell address generated. In a semiconductor memory which has, for example, a memory cell field in the form of a matrix, the column addresses are decoded in a second function block, a respective column line is selected by means of a column selection signal, and the data to be read out are amplified in a memory sense amplifier and transmitted outside of the memory cell field. There, they are usually fed to a further memory sense amplifier. In a third function block, a data signal which is to be read out is transmitted by this memory sense amplifier to an internal memory circuit or to an output buffer of the integrated memory, for example.
To enable a data signal which is to be read out to be transmitted to an internal memory circuit or an output buffer it is possible, for example, to use a data line pair with states which are differential with respect to one another. Here, one of the two lines has a signal crossover in each read cycle. As soon as the crossover is saved in a memory circuit, appropriate charging of the respective other line takes place in a known manner. This configuration requires a comparatively large amount of space on the semiconductor memory.
The data signal which is to be read out can alternatively be transmitted on a single static data line. This signal line, which connects the memory sense amplifier and either the internal memory circuit or the output buffer, has at most one signal crossover for each read cycle. In order to obtain the shortest possible access times, it is necessary to optimize both types of signal crossovers (for example "log. 0"=L to "log. 1"=H, "log. 1"=H to "log. 0"=L) in terms of their switching times. The minimum access time is limited here to the slower signal crossover of the two signal crossovers.